Altera Quartus II version 14.1 Update1

Altera Quartus II software version 14.1 featuring expanded support for Arria 10 FPGAs and SoCs, the FPGA industry’s only devices with hardened floating point DSP blocks and the industry’s only 20 nm SoC FPGAs that integrate ARM processors.

Altera’s latest software release provides immediate support for the hardened floating point DSP blocks integrated in Arria 10 FPGAs and SoCs. Users can choose between three unique DSP design entry flows and achieve up to an industry-leading 1.5 TFLOPS of DSP performance. The software also includes several optimizations that improve designer productivity by accelerating Arria 10 FPGA and SoC design time.

Integrated IEEE 754-compliant, floating-point DSP blocks in Arria 10 FPGAs and SoCs deliver unparalleled levels of DSP performance, designer productivity and logic efficiency. The Quartus II software version 14.1 offers an advanced tool flow with multiple design entry options that target the hardened floating point DSP blocks and allow users to quickly design and deploy solutions that address a range of computationally intensive applications, in areas such as high-performance computing (HPC), radar and medical imaging. These design flows include OpenCL for software programmers, DSP Builder for model-based designers and hardware description language (HDL) flows for traditional FPGA designers. Unlike a soft implementation, hardened floating point DSP blocks do not consume valuable logic resources for floating point operations.

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