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HDL Designer Series (HDS) 2018.2

Altium Designer HDL Designer DipTrace Sigrity and Systems Analysis Altium Nexus Allegro OrCAD free download PADS ORCAD Moldesim Xilinx FPGA

cadcamaec@protonmail.com2023-09-25EDA.PCB.CAM92

HDLDesignerSeries(HDS)2018.2,afamilyofpointtoolsforcomplexVerilog,VHDL,ormixed-langua

HDL Designer Series (HDS) 2018.2, a family of point tools for complex Verilog, VHDL, or mixed-language design.

What’s New in HDL Designer Series 2018.2 - December 2018:

Summary

HDL Designer
— Microsemi Libero Integration
— ModuleWare library enhancement
. Enhanced VHDL package support for selected ModuleWare components
SVAssistant
— Compilation flow speedup; 6x faster
— Performance improvements
— Advanced templates for “Extend This Class”
. Can include template files within template project e.g. SV_class.svt
— Several parser enhancements
— Java 8 upgrade
— Eclipse Neon 4.6.3 and CDT 9.2.1 upgrade
DesignChecker
— Capacity improvement
. Memory footprint optimization; reduced up to 50% measured on selected customer designs
— Batch flow enhancements
. Auto detection of design unit names in the hierarchy in basic batch flow
. Re-run analysis from UI after loading batch results database
— DesignChecker base rules help is now integrated with InfoHub
— Several parser enhancements
Register Assistant
— RTL Verilog pipelining support
— Java 8 upgrade
— Eclipse Neon 4.6.3
Quality
— >70 Defects & Enhancements Resolved