NI LabVIEW NXG 4.0 FPGA Module

NI LabVIEW NXG 4.0 FPGA Module helps you develop and debug custom hardware logic that you can compile and deploy to NI FPGA hardware.

New Features and Changes - Date: August 9, 2019

New Features
- Accessing memory items outside a Clock-Driven Loop—Use the new Read Memory (G Dataflow) and Write Memory (G Dataflow) nodes to read or write data to a memory item outside a Clock-Driven Loop.
- Accessing registers outside a Clock-Driven Loop—Use the new Read Register (G Dataflow) and Write Register (G Dataflow) nodes to read or write data to a register outside a Clock-Driven Loop.
The following nodes include error in and error out terminals:
- Read Memory (Clock-Driven Logic)
- Write Memory (Clock-Driven Logic)
- Read Register (Clock-Driven Logic)
- Write Register (Clock-Driven Logic)

Behavior Changes
The following I/O Channels nodes have non-functional terminals removed:
- Read I/O (Clock-Driven Logic)—The valid output is removed.
- Set Output Data (Clock-Driven Logic)—The ready output is removed.
- Set Output Enable (Clock-Driven Logic)—The settled output is removed.
The LabVIEW NXG FPGA Module is no longer required to perform the following tasks:
- Access FPGA targets in the Design view palette of SystemDesigner
- View or edit FPGA code
- Deploy bitfiles (.lvbitx) to FPGA targets
- Migrate LabVIEW FPGA functions to LabVIEW NXG
The LabVIEW NXG FPGA Module and relevant drivers are required to perform the following tasks:
- Use driver-specific features in your FPGA code
- Run or compile FPGA code
- Migrate LabVIEW FPGA code that relies on specific drivers to LabVIEW NXG

LabVIEW NXG 4.0 FPGA Module Known Issues

This document contains the LabVIEW NXG 4.0 FPGA Module known issues that were discovered since the release. Not every issue known to NI will appear on this list; it is intended to only show the severe and more common issues that can be encountered.

744863 - Errors outside of Clock-Driven Logic can incorrectly refer to the source of the error as an Optimized FPGA VI.
Some errors outside of Clock-Driven Logic can incorrectly refer to "Optimized FPGA VI" as the source of the error. One example is an un-initialized shift register on a For Loop

LabVIEW FPGA is a software add-on for LabVIEW that you can use to more efficiently and effectively design FPGA-based systems through a highly integrated development environment, IP libraries, a high-fidelity simulator, and debugging features. You can create FPGA VIs that combine direct access to I/O with user-defined LabVIEW logic to define custom hardware for applications such as digital protocol communication, hardware-in-the-loop simulation, and rapid control prototyping. Though the LabVIEW FPGA Module contains many built-in signal processing routines, you can also integrate existing hardware description language (HDL) code as well as third-party IP.

The LabVIEW NXG FPGA Module is the next generation of LabVIEW FPGA and contains only a subset of the features and hardware support in the LabVIEW 2018 FPGA Module.