Industrial Automation & Electrical
NI LabVIEW NXG 5.0 FPGA Module
NI LabVIEW NXG 5.0 FPGA Module. This Module enables engineers and scientists to develop, debug, and deploy custom FPGA code for NI hardware with user-programmable FPGAs.
New Features and Changes - Date: May 19, 2020
Refer to the list below to learn what's new or changed in the LabVIEW NXG 5.0 FPGA Module.
New Features
- Support for C series FPGA targets—Use the new Read Write I/O (G Dataflow) and Read Write I/O (Clock-Driven Logic) nodes to perform FPGA I/O operations on C series FPGA targets outside or inside a Clock-Driven Loop. Use the new Set Output Enable (G Dataflow) node to determine whether to allow the C series digital input and output resource to write data outside a Clock-Driven Loop.
- Accessing local FIFOs outside a Clock-Driven Loop—Use the following new FIFO nodes to manipulate FIFO data outside a Clock-Driven Loop:
. Clear FIFO (G Dataflow)
. FIFO Property (G Dataflow)
. Flush FIFO (G Dataflow)
. Peek FIFO (G Dataflow)
. Read FIFO (G Dataflow)
. Write FIFO (G Dataflow)
The LabVIEW NXG FPGA Module is the next generation of LabVIEW development software for FPGAs. The module provides an integrated development environment, easy hardware and resource organization, and improved simulation and debugging features to help you more easily program FPGAs. You can create FPGA VIs to define custom hardware for tasks such as digital signal processing, closed-loop control, digital protocol communication, and fault detection. You can also use the LabVIEW NXG FPGA Module to integrate existing hardware description language (HDL) code as well as third-party IP.
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