Xilinx Vivado Design Suite 2019.1

Vivado® Design Suite HLx Editions include Partial Reconfiguration at no additional cost with the Vivado HL Design Edition and HL System Edition. In-warranty users can regenerate their licenses to gain access to this feature. Partial Reconfiguration is available for Vivado WebPACK™ edition at a reduced price.

The new HLx editions supply design teams with the tools and methodology needed to leverage C-based design and optimized reuse, IP sub-system reuse, integration automation and accelerated design closure. When coupled with the UltraFast™ High-Level Productivity Design Methodology Guide, this unique combination is proven to accelerate productivity by enabling designers to work at a high level of abstraction while facilitating design reuse.

Accelerating High Level Design
Software-defined IP Generation with Vivado High-Level Synthesis
Block-based IP Integration with Vivado IP Integrator
Model-based Design Integration with Model Composer and System Generator for DSP

Accelerating Verification
Vivado Logic Simulation
Integrated Mixed Language Simulator
Integrated & Standalone Programming and Debug Environments
Accelerate Verification by >100X with C, C++ or SystemC with Vivado HLS
Verification IP

Accelerating Implementation
4X Faster Implementation
20% Better Design Density
Up to 3-Speedgrade Performance Advantage for the low-end & mid-range and 35% Power Advantage in the high-end

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