Xilinx Vivado Design Suite 2023.1.2

Xilinx Vivado Design Suite 2023.1.2 is a software suite for the design, synthesis and analysis of HDL for its line of FPGAs and SoCs.

AMD Vivado ML Edition - What's New in 2023.1.2 Key Highlights

Speed file Updates :
-1MP, -2MP, -2MHP, -3HP speed files in production for the following Versal HBM devices : XCVH1522, XCVH1542, XCVH1582
-1MP, -2MP, -2MHP, -3HP speed files in production for the following Versal Premium devices : XCVP1552
-1LP, -1LHP, -1MP, -2LP, -2LHP, -2MP, -2MHP, -3HP speed files in production for the following Versal Prime devices : XCVM2502
-1I, -1E, -1LI, -2E, -2LE, -2I speed files in production for the following Zynq UltraScale+ MPSoC devices: XCZU3TEG, XCZU3TCG
For customers using these devices, AMD-Xilinx recommends installing Vivado 2023.1.2. For other devices, please continue to use Vivado ML 2023.1.

Vivado Design Suite is a software suite designed by Xilinx for the design, synthesis and analysis of HDL for its line of FPGAs and SoCs. Vivado Design Suite includes many tools, like Vivado, Vitis, Vitis HLS and many others. The Vivado Design Suite offers many ways to accomplish the tasks involved in Xilinx FPGA design and verification. In addition to the traditional RTL to bitstream FPGA design flow, the Vivado Design Suite provides new system-level integration flows that focus on IP-centric design. Design analysis and verification is enabled at each stage of the flow. Design analysis features include logic simulation, I/O and clock planning, power analysis, timing analysis, design rule checking (DRC), visualization of design logic and implementation results, and programming and debugging. The entire solution is integrated within a graphical user interface (GUI) known as the Vivado Integrated Design Environment (IDE). The Vivado IDE provides an interface to assemble, implement, and validate the design and the IP. In addition, all flows can be run using the Tcl application programming interface (API). Tcl commands can be interactively entered using the Tcl prompt or saved in a Tcl script. You can use Tcl scripts to run the entire design flow, including design analysis, or to run just part of the flow